Our Processor for high embedded performance with RISC-V instruction-set compatibility, permit users to grasp the rich ecosystem of software and tools becoming available. This processor is interfaced with using the AMBA 2.0 AHB bus and supports the IP core plug & play method. It can be used with standard peripherals allowing development using RTOSs ported to RISC-V including such as FreeRTOS.
The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register files. This is a high-performance and flexible memory system which makes it ideal for applications such as AI, machine learning, networking, gateways, and smart IoT devices.
- Support for RV32IM
- RISC-V standard PLIC & PMP
- 3-stage pipeline
- Optional instruction and data cache
- JTAG debug
- Fully Coherent TileLink Bus
- Integrated 2MB L2 Cache with ECC
- CLINT for multi-core timer and software interrupts
- PLIC with support for up to 511 interrupts with 7 priority levels
- Hardware multiply-divide
- Hardware-based remote GDB
- 1.9 DMIPS/MHz
- Be differentiate with your proprietary enhancements and customizations to open source code modified by you or 3rd party RISC-V developers.
- You can save significant time by using a single processor architecture across all semiconductor platforms.
- You can make product independently of proprietary IP companies by owning source code to processor cores.
- Integration Guide covering:
- Place and Route
- Constraints File (SDC)
- Test simulation environment
- To access more than 4GB address space, in application areas like SSD and enterprise storage, or MAC layer protocol processing in wireless networking this can be used.