64-channel digital down-conversion (DDC) core

Features

• 64 independent downconversion channels
• Support for two 16-bit ADC inputs up to 140MS/s
• Alias-free channel bandwidths, up to 437.5 kHz
• Independent tuning of channel centre frequencies with a resolution <0.01Hz
• Fraction resampler for setting output sample rates
• Reconfigure channels without affecting operation of other channels
• End-to-end dynamic range of 80dB
• Gain control

Benefits

• Fits within a single Xilinx Virtex II Pro 30
• Replaces up to 16 four-channel DDC ASICs
• At least 8-times more silicon efficient than standard DDC cores
• Bit-true Matlab models for system simulations
• Custom versions available optimised to application

Deliverables

• ChannelCore64 is supplied as an EDIF netlist, and includes a VHDL model and test bench, and a bit-true Matlab model. The standard core is designed for use with Xilinx Virtex II Pro FPGA devices, and fits comfortably within an XC2VP30. Variants of the core can be provided for other FPGA families including Xilinx Virtex 4 and Altera Stratix II.
• Variants of ChannelCore64 can be produced upon request to meet a specific channelisation requirement. Please contact us if you have a specific requirement that you would like to discuss.

Block Diagram of the 64-channel digital down-conversion (DDC) core IP Core

• see the entire 64-channel digital down-conversion (DDC) core datasheet
• get in contact with 64-channel digital down-conversion (DDC) core Supplier