The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation). The encoder and decoder functions are completely independent and packaged as two sub-cores, CEC1-66/2112E and CEC1-66/2112D respectively. Decoder corrects a single burst error of upto 11 bits.
- Small Size
- Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
- 10G/40G/100G Ethernet MAC-friendly interface
- Practically self-contained: requires only memory for one 2112-bit block in the decoder.
- Flow-through design; low latency
- Synthesizable Verilog RTL source code (VHDL option available)
- Verilog Testbench
- Vectors for Testbench
- Expected results
- User Documentation
Block Diagram of the 66/2112 Codec for Cyclic Code (2112,2080) IP Core