6G Multi-protocol SerDes PHY

Features

• Duplex lane configurations of x1, x2, x4, and x21
• Transmit swing of at least 800 mV differential peak-to-peak
• Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
• BER of less than 10-15 at 6.375 Gbps
• Built-in Self Test (BIST) with ATPG and AC/DC boundary scan supportReceive linear equalizer with programmable settings providing up to 8dB gain at 6.4GbpsOperation across a wide temperature range (-40 C to +125 C)Receive linear equalizer with programmable settings providing up to 8dB gain at 6.4GbpsFlexible ASIC clocking

Benefits

• Duplex lane configurations of x1, x2, x4, and x8
• Transmit swing of at least 800 mV differential peak-to-peak
• Support for AC-coupled interfaces
• Fine-grain power up/down capability for power optimization, and ability to turn off unused link(s)
• BER of less than 10-15 at 6.375 Gbps
• Wide range of PLL multiplication options supporting low reference clock frequencies
• Flexible ASIC clocking
• Tight skew control of 2UI between lanes of the PMA
• One-tap transmit equalizer with multi-level de-emphasis; Supports PCIe and CEI6-SR de-emphasis settings
• Receive linear equalizer with programmable settings providing up to 8dB gain at 6.4Gbps
• Expandable register interface enabling communication with multiple PMAs and PCS-BIST soft macros
• Built-in Self Test (BIST) with ATPG and AC/DC boundary scan support
• Built-in PRBS pattern generation and checking for standalone loopback testing
• In-situ real-time monitoring and receive data eye schmoo
• Operation across a wide temperature range (-40 C to +125 C) 4.976 - 6.375

Deliverables

• PMA Hard Macro
• PCS-BIST Soft Macro
• Datasheet
• SoC integration guide
• Optional design integration and bring-up support services

Applications

• Server/Storage/Networking

Block Diagram of the 6G Multi-protocol SerDes PHY IP Core

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