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6G PHY in TSMC (16nm)
The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys’ highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) cost, low-power consumption in consumer applications. The multi-protocol 6G PHY IP provides low active and standby power while exceeding signal integrity and jitter performance of PCI Express 2.1, SATA 6G, SGMII, XAUI, and CEI-6G specifications. The PHY incorporates advanced power saving features such as PCI Express L1 sub-states power management and power gating in standby mode of operation.
The hybrid transmit drivers support low power voltage mode and high swing current mode for further active power savings. The PHY’s Automatic Test Equipment (ATE) capabilities and wirebond packaging reduce the overall BOM cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.
The hybrid transmit drivers support low power voltage mode and high swing current mode for further active power savings. The PHY’s Automatic Test Equipment (ATE) capabilities and wirebond packaging reduce the overall BOM cost. The embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates seamlessly with the DesignWare Physical Sublayers and digital controllers/media access controllers (MACs) to reduce design time and to help designers achieve first-pass silicon success.
Features
- Optimized for low power and small area
- Includes one, two or four full-duplex transceivers (transmit and receive functions)
- Physical coding sublayer (PCS) blocks for PCIe, SATA, and XAUI, supporting backchannel initialization, and power management
- Multi-lane PHY shares a single clock and support core
- Provides high-speed serial and low-speed parallel clocks to both the transceiver and PCS
- Supports both internal and external reference clock connections to the PHY
- Multi-featured transmitter and receiver equalization
- Supports chip-to-chip, port side and backplane interfaces
- Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths
- Contains embedded pseudo random bit sequencer (PRBS) for internal and external loopbacks
- Fully controllable via the integrated logic core and the test access port (TAP)
- Embedded bit error rate (BER) tester and internal eye monitor
Benefits
- Supports 1.25 to 6.25 Gbps data rates
- Multi-lane PHY supporting x1, x2, and x4 macro configurations
- Supports PCI Express 2.1, SATA 6G, SGMII, XAUI, CEI-6G specifications
- Supports x1 to x16 macro configurations
- Superior signal integrity enabled by adaptive continuous time linear equalizer (CTLE) and Feed Forward Equalization (FFE)
- Lowest active and standby power supporting power management, power gating, and novel transmission design
- Spread Spectrum Clock (SSC)
- Reference clock sharing for aggregated macro configurations
- Supports IEEE 1149.6 AC Boundary Scan
- Wirebond or flipchip packaging with flexible bumps
- Supports -40°C to 125°C Tj
Deliverables
- Verilog models
- Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
- GDSII
- ATPG models
- HSPICE/IBIS-AMI models
- Documentation
Applications
- Consumer
- Mobile
- Storage (SSD, HDD)
- Power-sensitive applications
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PCI Express PHY
- PCI Express (PCIe) Gen4 x4
- PCI Express (PCIe) Gen4 x8
- Complete PCIe 4.0 Soft IP supporting endpoint, root port, switch, bridge and advanced features such as SR-IOV, multi-function, data protection (ECC, ECRC), ATS, TPH, AER and more
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- PCIe 5.0 Controller
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface