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7 track Ultra High Density standard cell library at TSMC 28 nm HPC+
TSMC 28 HPC+, SESAME uHD for ultra high-density logic design thanks to a low track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
Features
- Configuration
- 7 track library with minimum length (L=30 nm)
- Reach the highest density
- Hand tuned cells, designed with 7-Track for optimal area reduction
- Pulsed latches as Spinner Cells instead of flip-flops: for min. 30% gain in density
- Metal 1 power rails / Metal 1 and 2 used for cells designIdeal for slow to medium speed logic blocks
- 5% up to 15% denser after P&R than standard 7-Track library
- Extend battery life
- Operating voltage level @ 0.9 V +/-10%
View 7 track Ultra High Density standard cell library at TSMC 28 nm HPC+ full description to...
- see the entire 7 track Ultra High Density standard cell library at TSMC 28 nm HPC+ datasheet
- get in contact with 7 track Ultra High Density standard cell library at TSMC 28 nm HPC+ Supplier
standard cell IP
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 12 track thick oxide standard cell library at TSMC 40 - low leakage and direct battery connection (operating voltages from 1.1 V to 3.3 V)
- 7 track Ultra High Density standard cell library at TSMC 28 nm
- 6 track High Density standard cell library at TSMC 55 nm