7 track Ultra High Density standard cell library at TSMC 28 nm
Features
- Configuration
- 7 track library with minimum length (L=30 nm)
- Reach the highest density
- Hand tuned cells, designed with 7-Track for optimal area reduction
- Pulsed latches as ?Spinner Cells? instead of flip-flops: for min. 30% gain in density
- Metal 1 power rails / Metal 1 and 2 used for cells design
- Ideal for slow to medium speed logic blocks
- 5% up to 15% denser after P&R than standard 7-Track library
- Extend battery life
- Dual voltage characterization to support a wide operating voltage range from 0.9 V +/-10% to 0.6 V +/-10%
View 7 track Ultra High Density standard cell library at TSMC 28 nm full description to...
- see the entire 7 track Ultra High Density standard cell library at TSMC 28 nm datasheet
- get in contact with 7 track Ultra High Density standard cell library at TSMC 28 nm Supplier
standard cell
- DesignWare HPC Design Kit contains high-speed and high-density memory instances and standard cell libraries
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