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Switching regulator, inductor-based, PWM mode, high efficiency
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8-10 bit SAR ADC SMIC
The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 10-bit resolution at sample rates up to 20 MSps. It includes an eight-channel input multiplexor. Some inputs will be buffered inside the ADC, whereas others will bypass the buffer and be connected directly to the ADC to provide full rail-to-rail capability..
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Block Diagram of the 8-10 bit SAR ADC SMIC IP Core
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