The DF6811 is an advanced 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. DF6811 soft core is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller. It has an improved FAST architecture, that is approximately 4 times faster, compared to original implementation. In the standard configuration, the core has integrated on chip, major peripheral functions. The Core can be provided in configurations, that match the following:
There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system, has three input capture lines, five output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem, can count external events, or measure external periods.Self-monitoring circuitry is included on-chip, to protect against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit, provides a non-maskable interrupt, if illegal opcode is detected.Two software-controlled power-saving modes - WAIT and STOP, are available to conserve additional power. These modes make the DF6811 IP Core especially attractive for automotive and battery-driven applications.
The DF6811E Microcontroller Core can be equipped with the ADC Cotroller, allowing use of external ADC Controller with standard ADC software. The ADC Controller makes external ADC's visible as internal ADC's in original 68HC11E Microcontrollers. The DF6811E has built-in real time, on-chip hardware debugger - DoCD , allowing easy software debugging and validation. The DF6811E is fully customizable - it is delivered in the exact configuration to meet users requirements. There is no need to pay extra, for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's DF68XX Core, has a built-in support for DCD Hardware Debug System, called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.
- FAST architecture, 4 times faster than the original implementation
- Software compatible with industry standard 68HC11
- 10 times faster multiplication
- 16 times faster division
- 256 bytes of remapped System Function Registers space (SFRs)
- De-multiplexed Address/Data Bus, to allow easy memory connection
- Core can also be used without I/O wrapper, so each peripheral functions pins will be separated from I/O ports lines.
- Two power saving modes: STOP, WAI
- Ready pin allows Core to operate with slow program and data memories.
- Fully synthesizable
- Static synchronous design
- No internal reset generator or gated clock
- Positive edge clocking and no internal tri-states
- Scan test ready
- 1 GHz of virtual clock frequency compared to original implementation
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF netlist
- VHDL & VERILOG test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery the IP Core updates, minor and major versions changes
- Delivery the documentation updates
- Phone & email support