The D68HC11K is synthesisable soft IP Core Microcontroller, fully compatible with the Motorola MC68HC11K industry standard. It can be used, as a direct replacement for the following microcontrollers:
In standard configuration, the core has integrated on-chip major peripheral functions. An asynchronous serial communication interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem, can count external events or measure external periods. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory, to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Self-monitoring, on-chip circuitry, is included, to protect D68HC11K against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit, provides a non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes - WAIT and STOP are available, to conserve additional power. These modes, make the D68HC11K IP Core especially attractive for automotive and battery-driven applications.
The D68HC11K Microcontroller Core, can be equipped with the ADC Cotroller, allowing use of external ADC Controller with standerd ADC software. The ADC Controller makes external ADC's visible, as internal ADC's in original 68HC11K Microcontrollers.
The D68HC11K has built-in, real time, on chip hardware on chip debugger - DoCD , allowing easy software debugging and validation.
The D68HC11K is fully customizable - it is delivered in the exact configuration, to meet users' requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
Each of the DCD's DF68XX and D68HC11X Cores, have built-in support for DCD Hardware Debug System, called DoCD . It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.
- Cycle compatible with original implementation
- Software compatible with 68HC11K industry standard
- I/O Wrapper, making it pin-compatible core
- SFR registers remapped to any 4KB memory page
- Two power saving modes: STOP, WAI
- Fully synthesizable
- Static synchronous design
- No internal tri-states
- Scan test ready
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF netlist
- VHDL & VERILOG test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery the IP Core updates, minor and major versions changes
- Delivery the documentation updates
- Phone & email support