The W65C02S IP is a 8-bit 65xx Microprocessor available in GDSII Hardcore, RTL Softcore, and FPGA Specific Firm Cores. This is a CMOS update of the original 6502 microprocessor. This was the first licensed microprocessor IP and has been used in a wide range of applications from radiation resistant hi-rel applications such as medical implantable life-support devices to ultra high volume consumer devices.
The 8-bit data bus based architecture provides a flexible interface to memories, peripherals and other IP blocks.
WDC's RTL Softcore version provides a cycle accurate option providing for implementation onto any foundry process.
Development tools are available for creation of 65xx application code.
- 8-bit data bus
- 8-bit ALU, Accumulator, Stack Pointer, Index Registers, Processor Status Register
- 16-bit Program Counter
- 69 instructions
- 16 addressing modes
- 212 Operation Codes (OpCodes)
- 16-bit address bus provides access to 65,536 bytes of memory space
- Vector Pull (VPB) output indicates when interrupt vectors are being addressed
- WAit-for-Interrupt (WAI) and SToP (STP) instructions reduce power consumption, decrease interrupt latency and enable synchronization with external events
- Variable length instruction set enables smaller code optimization over fixed length instruction set processors. consuming low power
- Flexible Licensing Options and Pricing Model
- GDSII Database, Verilog RTL, or FPGA Specific Post-Synthesis Netlist
- Simulation Test Benches, Results, and Documentation
- Assemly Test Files
- Datasheet Documentation