The S3DACMPTD8C90 combines eight low-power programmable threshold comparators where the programmable thresholds are implement using eight digital-to-analog converters (DACs) which drive the comparator inverting inputs so the that individual trip thresholds can be digitally set. Each programmable threshold is also available externally by means of interchanging them with the comparator inputs.
Each comparator goes high when its analog input exceeds its digitally set threshold.
The DAC is implemented using a current steering architecture which drives current into a resistive load.
- 90nm TSMC Logic LP Process, 6 Metals Used (No Analog Options)
- 1.2V and 3.3V Power Supplies
- 8-Bit Voltage DAC resolution
- Comparator Input Range 0-2.5V
- DAC output range 0-1.25V
- Power Dissipation < 8mW
- Power-Down Mode
- Compact Die Area:0.5mm2
- This 8-bit Voltage DAC features an excellent static performance that includes ±0.5LSB DNL and ±1LSB INL.
- The S3DACMPTD8C90 is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- Power-Supply Monitors
- Alarm Limit Detectors
Block Diagram of the 8-Channel Comparator with Programmable Thresholds IP Core