The device is a t2-channel intermediate-frequency amplifier (IFA). Each channel consists of 1 stage amplifier with differential inputs/outputs, programmable gain and offset voltage setting. Input/output tuned capacitors together with IFA input/output impedance create 2nd order LPF. Signal reception mode with 8 kHz bandwidth requires external 2 nF capacitor. Analog compensation system is used to reduce IFA output offset voltage. There is an option of voltage reference levels former for ADC.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
- iHP SGB25V
- Wide gain range 0…43 dB
- Tunable bandwidth 8…512 kHz
- Output offset voltage digital setting more than +/- 50 mV
- Input offset voltage analog compensation in the range -50…+ 50 mV
- Input impedance 20 kOhm
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)