The 800 Gigabit Ethernet Base-R PCS Core follows the 400G IEEE 802.3bs standard and is designed to be used in conjunction with the MorethanIP 800 Gigabit Ethernet MAC Core to create flexible system solutions.
On the line side, the PCS implements eight 96-, 128- or 160-Bit Serdes Lanes that can be connected to any industry standard 106.25Gbps or, for an increased bandwidth, faster Serdes.
The PCS implements the Reed Solomon RS(544,514) FEC structure compliant with IEEE802.3bs Clause 119 with RS-FEC codewords interleaving. The PCS RS-FEC is also optimized for low latency.
The PCS in 800Geth mode aligns and re-arranges swapped Serdes lanes and deskew over 32 Virtual Lanes (VLs).
The 800G PCS Core implements a 1024-Bit wide 800GMII (800Gbps Media Independent Interface) to MorethanIP or third party 800Geth MAC.
The 800Geth PCS Core can be configured to implement two independent 200G or 400G interfaces for flexible dynamic rate systems and backward compatibility with existing lower rate interfaces.
For efficient line monitoring and debug, the PCS implements multiple line status information and error counters accessible with a 16-Bit generic or APB control interface.
Block Diagram of the 800 Gigabit Ethernet Base-R PCS Core IP Core