The RF transceiver IP is a complete radio front-end optimized for sub-GHz band, IEEE 802.11ah SoC implementation, based on the industry’s proven direct conversion transceiver
architecture. This transceiver IP has fully integrated power amplifiers along with the capability to support various commercial external FEM. RF IO ports are single-ended and a fractional-N synthesizer while the power amplifiers and LDOs are fully integrated for minimum BOM and PIN counts.
A special LPO for the high Sleep Clock Accuracy (SCA) is also integrated for the low power applications. This Radio IP supports various radio calibration functions such as TRX IQ mismatch calibration, LO feedthrough calibration, DC offset cancellation, fast AGC, VCO calibration, VCO temp
variation compensation, bias calibration, LPF corner frequency compensation, battery monitoring, and temperature monitoring.
The internal, digitally-controlled gain stages at the RF and BB levels provide both low noisefigure and large dynamic range of the receiver. Furthermore, the transmitter has more than30dB gain range, which provides a wide output power range. Cutoff frequency of the baseband filters are calibrated with an internal RC compensation scheme while the low pass filter supports modulation bandwidths up to 16MHz. A crystal oscillator, which is connected to a low cost external crystal, is also integrated. The SPI interface controls most of the transceiver functions.
- Low power sub-GHz band transceiver for IEEE 802.11ah
- Compliant with IEEE 802.11ah draft 5.0
- Support up to 16MHz channel BW
- TX LOFT/IQ mismatch calibration
- Modulation: BPSK, QPSK, 16QAM, 64QAM
- EVM: < -31dB @ 64QAM
- Hard macro containing IEEE 802.11ah radio
- Integration support with baseband
Block Diagram of the 802.11 AH Sub 1 Ghz RF IP IP Core