The S3AFE802ACT28 is a low-power, low die area MIMO AFE for Wireless broadband applications such as 802.11ac. The AFE can be customizable for numerous configurations such as 1x1, 2x1, 2x2. The default configuration which is 1x1 as shown includes ultra-low power SAR IQ ADC and a current steering IQ DAC.
The clocks for the ADC and DAC are generated by a versatile low jitter integer mode PLL integrated as part of the AFE.
A 10-bit ADC and an 11-bit DAC are also included to perform auxiliary functions.
The S3AFE802ACT28 operates from a 0.9V/1.8V supply, and each of the components uses architectures ideally suited for fabrication in a 28nm CMOS process and in complex SoCs.
The S3AFE802ACT28 does not require any special analog options, and can be cost-effectively ported across foundries, different MIMO configurations and process nodes upon request.
- 28nm Process, 6 Metals Used
- No Analog Options
- Customizable AFE
- 1.8V and 0.9V Supplies
- Sampling Rate up to 160MS/s
- 12-bit 160MS/s IQ ADC
- 12-bit 320MS/s IQ DAC
- Low-Jitter Integer-N PLL
- Input Signal Swing 1.0Vppdiff
- 10.1-bit ENOB Typ.@ Fin= 40MHz
- SFDR=65dBc Typ. @ Fout= 40MHz
- Internal Bandgap and Biasing System Included
- No External Components Required
- Stand-By and Power-Down Modes
- Ultra-Low Power Dissipation:
- Ultra-Low Die Area
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (VHDL/Verilog)
- Integration Support
Block Diagram of the 802.11ac Analog Front-End (28nm) IP Core