802.11ac Analog Front-End (40nm)
The default configuration which is 1x1 as shown includes ultra-low power SAR IQADC and a current steering IQDAC.
The clocks for the ADC and DAC are generated by a versatile low jitter integer mode PLL integrated as part of the AFE.
A 10-bit ADC and an 11-bit DAC are also included to perform auxiliary functions.
The S3AFE802ACT40 operates from a 1.1V/2.5V supply, and each of the components uses architectures ideally suited for fabrication in a 40nm CMOS process and in complex SoCs.
The S3AFE802ACT40 does not require any special analog options, and can be cost-effectively ported across foundries, different MIMO configurations and process nodes upon request.
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Block Diagram of the 802.11ac Analog Front-End (40nm) IP Core
