The so_ip_8051C256 is a soft core of a 8-bit CPU dedicated for operation with fast (on-chip) and slow (off-chip) memories.
So_ip_8051C256 soft core is 100% binary compatible with the CPU from industry standard 8051 microcontroller. It executes all ASM51 instructions and has the same instruction set as the 8031.
The so_ip_8051C256 serves both software and hardware interrupts.
So_ip_8051C256 has an advanced architecture that enables it to be 4.51 times faster than the CPU from original 8051 microcontroller.
So_ip_8051C256 is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_8051C256 is a microcode-free design developed for reuse in FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
- 100% software compatible with industry standard 8051
- Advanced architecture enables to execute instructions on average 4.51 times faster compared to original 8051
- 8 times faster multiplication
- 8 times faster division
- 4 times faster addition
- 256 bytes of internal (on-chip) Data Memory
- Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
- Up to 64K bytes of internal (on-chip) or external (off-chip) Data Memory
- De-multiplexed Address/Data bus to allow easy connection to memory
- Fully synthesizable synchronous design with positive edge clocking and no internal tri-states
- Interrupt Controller with 2 priority levels and 2 external sources
- Four 8-bit I/O Ports
- Separate input and output lines
- VHDL Source Code or netlis
- Verification environment with regression suite
- Technical documentation
- Installation notes
- User Manual
- Instantiation templates
- Reference Design
- Technical Support
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support