The DB8051C contains Digital Blocks DB8051C CPU Core and contains standard 8051 MCU peripherals, including an interrupt controller, UART Serial Port, two 16-bit timers, and four 8-bit I/O ports. Streamlined for ASIC, ASSP & FPGA Integration, the RTL microarchitectural choices include Registered RAMs, Hardware Micro Control Unit, Unidirectional Busses, & a Fully Static, Rising Edge Only, Synchronous Design.
- 8-bit Microcontroller Binary Compatible with MCS 51 Instruction Set
- Standard 8051 Architecture: Arithmetic / Logical Unit, Hardware Multiply / Divide, Boolean Processor for Bit Manipulation, 5 Addressing Modes
- Enhanced 8051 Architecture: minimum 3 Cycles Per Instruction Execution
- Up to 256 bytes of internal Data Memory
- Program Memory: User Defined, up to 64 KB; NVM or Configurable SRAM
- Data Memory: User Defined, up to 64 KB
- Standard Peripherals: interrupt controller, UART Serial Port, two 16-bit timers, and four 8-bit I/O ports
- Power Management Unit
- Streamlined ASIC & ASSP & FPGA Integration: Registered RAMs, Hardwired (No RAM) Micro Control Unit
- Fully synthesizable, static synchronous design, single edge clocking, and no internal tri-states. Scan test ready
- The DB8051C-FSM Microcontroller is a silicon-proven industry standard 8051microcontroller. The 8051addressing modes (register, direct address, indexed, immediate) enable smaller program code size, thus requring less Program Memory than alternative microcontroller architectures. Digital Blocks' microarchitecture design allows for small area requirements.
- Verilog RTL Source.
- Comprehensive testbench suite with expected results.
- Synthesis scripts.
- Installation Guide.
- Technical Reference Manual.