The DB8051C-FSM is ideally suited for programmable, complex FSM implementations, with its 8-bit architecture and 255 instructions, which include Arithmetic, Logical, Boolean Bit Manipulation, Data Transfer, & Program Branching. The Boolean Processor is for single bit data manipulation, and the Arithmetic Unit’s multiply/divide instructions consume a very low VLSI footprint. For fast program data storage & manipulation, the DB8051C contains an integrated 128/256 byte SRAM. Optionally, the user can add up to 64 KB of Data Memory. Through user selectable 1-800 GPIO, the FSM interfaces with the external logic under control.
- 8-bit Microcontroller Binary Compatible with MCS-51 Instruction Set
- Standard 8051 Architecture: Arithmetic / Logical Unit, Hardware Multiply / Divide, Boolean Processor for Bit Manipulation, 5 Addressing Modes
- Enhanced 8051 Architecture: minimum 3 Cycles Per Instruction Execution
- Streamlined ASIC & ASSP & FPGA Integration: Registered RAMs, Hardwired (No RAM) Micro Control Unit
- Program Memory - user defined, up to 64 KB; NVM or Configurable SRAM
- Data Memory - user defined, up to 64 KB
- General Purpose I/O (GPIO) for Finite State Machine Inputs / Outputs
- Optional Peripherals - Contact Digital Blocks
- The DB8051C-FSM Microcontroller is a silicon-proven industry standard 8051microcontroller. For complex Finite State machine design, the DB8051C-FSM release offers a high-level instruction set with a small VLSI footprint. The 8051addressing modes (register, direct address, indexed, immediate) enable smaller program code size, thus requring less Program Memory than alternative microcontroller architectures.
- Verilog RTL Source
- Comprehensive testbench suite with expected results
- Synthesis scripts
- Installation Guide
- Technical Reference Manual