The block is second order delta-sigma ADC with 5-level quantizer.
The block consists of:
- two integrating cascades based on switch capacitors technique;
- 5-level flash-ADC;
- tunable (6-bit control) clock signal frequency divider;
- clock splitter;
- block of bias currents, tunable (6-bit control);
- Data-Weighted Averaging (DWA) correction of capacitors mismatch;
- input signal level detection.
Output signal is represented in “thermometer” code. There is a possibility to disable of each channel, frequency divider, block of bias currents, DWA correction. There is an in-built output from frequency divider for clocking digital filters.
Input DC level is 0.9 V; recommended voltage levels for references are 0.9 ± 0.4 V; recommended input signal differential amplitude is 0.64 V; allowable deviation of clock duty cycle: 50 ± 5%.
The block is fabricated on iHP SiGe BiCMOS 0.25 um (SGB25V) technology.
- iHP SGB25V
- 2-channel wide-band delta-sigma ADC
- 9-bit resolution
- Information speed modes: 2.4 kBd – 512 kBd
- Supply voltage 1.8 V
- Tunable opamps current
- SFDR > 63 dB
- SNR > 60 dB
- Input differential signal range 1.6 V
- In-built input signal level detection, sign detection
- Supported foundries: TSMC, UMC, Global Foundries, SMIC, iHP, AMS, Vanguard, SilTerra
- Schematic or NetList
- Abstract model (.lef and .lib files)
- Layout view (optional)
- Behavioral model (Verilog)
- Extracted view (optional)
- DRC, LVS, antenna report
- Test bench with saved configurations (optional)
- Analog to digital conversion of wide-band input signal
- Recievers, transmitters, transceivers
- Analog integral circuits
- Measuring equipment
- Medical equipment