9b-1.62Gsps I&Q ADC IP

A dual core I & Q Analog to Digital Converter based on the time interleaved SAR architecture. The IP includes a power supply regulator (LDO), integrated references and digital compensation (for gain, offset and skew). It works in a differential mode for analog input I & Q. The output data are organized in 12x12b–buses clocked at 135MHz (Fs/12). Each bus gives the data coming from a specific sub-ADC. A data ready clock is provided at 135MHz (Fs/12). The input buffers I & Q and the LDO are in G02. The Core ADC and the Digital Compensation are in GO1.

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