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A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
A key attribute of the Certus 28nm IO library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell set can be configured as input, output, open-source, or open-drain with an optional internal 60K ohm pull-up or pull-down resistor. Digital cells for 25MHz, 75MHz, and 150MHz allow optimization across SSO currents & power. ESD protection for VDDIO, VREF and core VDD supplies is constructed in an aggressive footprint. The library also features 5V I2C open-drain (fail-safe), a 5V OTP programming cell, and 1.8V & 3.3V analog cells. 1.8V LVDS and 3.3V, 5V tolerant fail-safe HDMI protection blocks with low-cap signal pads are also available. The library is enriched with feed-through, filler, transition and domain-break cells to allow for flexible pad ring construction.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus supports IO libraries across multiple TSMC nodes including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus supports IO libraries across multiple TSMC nodes including 180nm, 130nm, 40nm, 28nm, 22nm, and 16/12nm. Certus is particularly suited at providing custom variants in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Features
- General-Purpose IO
- Multi-voltage 1.8V / 3.3V switchable operation
- 25MHz, 75MHz, & 150MHz GPIO speed options
- Full-speed output enable
- Independent power sequencing
- Shorted output protection
- Schmitt trigger receiver
- 60KΩ selectable pull-up or pull-down resistor
- Fail-safe
- 2KV HBM, 500V CDM, 2KV IEC 61000-4-2
- I2C/SMBUS Open Drain I/O
- Up to 5V tolerant
- Output enable
- Hysteresis input
- Power-on sequence independence
- Fail-safe
- External resistor support of 1KΩ - 50KΩ
- ESD protection of 2KV HBM, 500V CDM
- Also DDC, CEC and HPD compliant
- ANALOG
- 1.8V & 3.3V tolerant options
- ESD protection of 2KV HBM, 500V CDM
- HDMI & LVDS protection Macros
- Power & Ground pads included
- Parasitic matching across differential signal pads
- Low-capacitance signal pads (<250fF)
- 5V tolerant (HDMI)
- Fail safe (HDMI)
- ESD protection of 2KV HBM, 500V CDM
- Footprint & metal stack options
- 55um x 75um, 6 metals
- 25um x 130um, 7 or 9 metals
- 20um x 186um, 9 metals
- Wirebond options
- 55um pitch, single inline
- 25um pitch, dual row staggered
- 20um pitch, triple row staggered
Benefits
- Area-efficient
- Dynamic multi-voltage operation
- Drive strength options
- Fail-safe
- Customizable
- Pull-up / pull-down resistor options
- Feature-rich
- Robust
- I2C open-drain & analog cells
- Cell pitch & metal stack options
- Silicon proven
Deliverables
- GDS
- CDL netlist
- Verilog stub
- Verilog behavioral model
- LEF
- Liberty Timing Files
- IBIS (option)
- Electrical datasheet
- User guide and application notes
- Consulting and Support
Applications
- 1.8V-3.3V GPIO, RGMII, 5V I2C/SMBUS, DDC, CEC, HPD, SD.
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