This dual channel Analog -to-Digital converter IP is based on a monolithic differential pipelined architecture with output error correction logic providing 12 bits conversion accuracy up to 80 Mhz sampling frequency.
It is designed for industry standard 0.18um 1P6M CMOS technology supplied at 3.3V.
This dual channel ADC can interface with both 1.8V or 3.3V core logic, by connecting dvdd to 1.8V or 3.3V power line, giving more flexibility for design reuse.
- • 12-Bits pipeline architecture
- • 40MS/s sampling rate
- • No missing code guaranteed
- • 2.0 Vp-p differential input
- • 3.3V +/-10% supply voltage, -40/+125 C temperature.
- • 1P6M layout structure based on 0.18um 1P6M 3.3V/1.8V generic logic process.
- • Fully differential architecture
- • Area: (contact us)
- • Power consumption [contact us]
- • Power down leakage current <1uA
- • Antenna diodes on each digital input.
- • uses MIM capacitor
- • can interface with both 1.8V and 3.3V core logic
- This dual channel ADC is suitable for :
- - Communication Receiver Channel (IF sampling)
- - Mobile TV
- - Digital Imaging/video
- - Graphic capture
- - Ultrasound Equipment
- LVS netlist
- LIB timing
- LEF abstract
- Verilog/VHDL model
- Application Notes