The Cadence Dual 7-bit, 3GSps ADC IP is a dual 7-bit ADC with differential inputs. Each ADC supports sustained conversion rates of 3GSps.
This Dual 7-bit, 3GSps ADC IP has clean, well-defined interfaces for easy incorporation into any analog front-end (AFE) or system-on-chip (SoC) design. A Cadence-standard Analog Test Bus is included to facilitate preproduction testing. Implemented on the TSMC 28HPC process, the Cadence ADC IP provides a cost-effective, power-efficient solution for demanding applications.
- Dual 7-bit, 3GSps Analog-to-Digital Converters
- Low power (typ. 162mW at 3GHz)
- Internal Reference Generator
- Analog test bus for preproduction testing
- Small footprint
- Multi-level power-down mode
- Dynamic power-saving features
- 8:1 data multiplexer
- Standard integration views—timing, physical views, LEF, DRC, LVS, ANT
- GDSII layout
- Complete documentation customized to your specific configuration