The GRAES core implements the Advanced Encryption Standard (AES) symmetric encryption algorithm for high throughput application (like audio or video streams). The implemented AES-128 algorithm is specified in the “Advanced Encryption Standard (AES)” document, i.e. Federal Information Processing Standards (FIPS) Publication 197. The document is established by the National Institute of Standards and Technology (NIST).
The GRAES core is accessed via an AMBA AHB slave interface. To facilitate high throughput and low latency, the core utilizes the AMBA AHB retry feature to indicate to the processor that an encryption/decryption is still ongoing and that the processor should retry its read access. Alternatively, the core provides an interrupt to indicate when the encryption/decryption of a 128-bit block is completed.
- AMBA AHB interface for AES-128 core
- AMBA AHB slave interface
- No block RAM needed
- Low CPU overhead due to burst transfers
- Low area consumption
- Compatible with AMBA-2.0
- Synplify project file
- VHDL test bench
- Template design for LEON3 processor
- FPGA evaluation board (optional)