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Advanced Encryption Standard (AES) core
The AES / Rijndael core can handle input block sizes of 128, 192 or 256 bit. The Decoder needs the key and the cipher text as input. The start_de signal signalise the beginning of a decryption. The input data is read and enciphered. After the plain text is build the plain data were wrote to the output and the ready_de signal signalised this.
Features
- Complete AES implementation to latest NIST FIPS-197
- 128 bit block size and configurable bit key size (128, 192 or 256 bit)
- Technology independent HDL model
- Simple external interface, easy adaptation
- Structured core design, acces to internal nodes
- Implementation for high data rate
- Implementation with or without key expansion
Benefits
- High Speed encryption, decryption
- UWB (Ultra Wide Band)
- WUSB, ECMA368, ECMA387
- SoC embedded applications
Deliverables
- HDL RTL code or net list for each required technology
- Testbench with functional test vectors
- User-Documentation
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Advanced Encryption Standard (AES) core IP
- Advanced Encryption Standard (AES-128) core with AMBA AHB interface
- Secure 128-bit Advanced Encryption Standard (AES) coprocessor
- Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
- Cryptographic library for encryption and decryption of Advanced Encryption Standard (AES) in ECB, CBC, OFB, CTR and GCM modes
- 128-bit Advanced Encryption Standard (AES) coprocessor
- Advanced Encryption Standard Module