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Advanced Encryption Standard En- / Decryption IP-Core
The Advanced Encryption Standard (AES) specifies an approved cryptographic algorithm that can be used to protect electronic data. It is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information.
Features
- Implementation of the Advanced Encryption Standard (AES) according to NIST FIPS PUB 197 with supported key length of 128 or 256 bits
- Support of different operating modes (ECB, CBC, CFB, CTR, OFB, GCM) according to NIST Special Publication 800-38A ’Recommendation for Block Cipher Modes of Operation’
- Support different input and output port widths (8, 16, 32, 64 or 128 bits) depending on employed mode of operation
- Available as encryption-only-, decryption-only- or encryption-and-decryption-core with or without included key schedule
- Implementation available for all Xilinx Virtex-Series-FPGAs, Altera Stratix II/III FPGAs, Actel ProAsic3/Axcelerator FPGAs
- Different optimization goals such as area and throughput availablE
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