The IPC-BL157A-ZM, Advanced Flash Controller Interface (AFCI) is a register level interface that allows software and hardware state machines the ability to communicate with a nonvolatile memory subsystem. The command communication, data movement, and status information are accomplished with a minimal number of non-cacheable read/writes. This is important to maximize throughput and minimize impact of register read/writes to the platform software.
Command information is managed utilizing a command submission and completion queue architecture which uses doorbell registers in the controller register set to communicate that a new command has been populated in the command queue. This queue is a circular buffer which can be as small as a depth of 2 and as large as a depth of 65536. This flexibility is important to manage system platform trade-offs of performance with system complexity.
Administrative commands are communicated using a secondary command submission and completion queue. This allows for two completely separate masters to issue command information to the controller. The intention here is to allow for the main data command information to use the command submission queue, and administrative/maintenance commands to be issued using the administrative queue. The arbitration scheme between the admin queue and the command queue can be set by system software.
The IPC-BL157A-ZM IP core is designed around a scalable port architecture which allows for parallel communication across a multitude of NAND devices. Each NAND port can be connected to one or more NAND Targets. The parallelized port architecture allows scalable capacity and performance to meet a wide variety of applications.
The IPC-BL157A-ZM is based on a paired Submission and Completion queue mechanism. The AFCI submission queue is a circular buffer where the producer of commands is either software or a hardware state machine external to the AFCI controller. The consumer of commands is the AFCI submission state machine. New command entries are reported to the AFCI submission state machine by a single, non-cacheable write to the AFCI controller registers. The command producer can arm as many commands as there is space in the command queue with a single register write.
The Advanced Flash Controller (AFCI) Interface core optionally supports AES-XTS under Part # IPC-BL157A-1-ZM and incorporates a 256 bit encryption level capable of data throughput greater than 20Gbps. The encryption algorithm used in the IPC-BL157A-1-ZM is FIPS-197 certified.