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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
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Aeonic Generate Digital PLL for multi-instance, core logic clocking
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality digital PLL that enables distributed clocking for per-core dynamic frequency scaling (DFS) and fine-grained clock tuning. It reliably supplies a clock signal to processing elements across a wide frequency range, using standard cells and operating on core voltage (VDD) for simplified integration. In addition, the Aeonic Generate™ CGM supplies design teams with clock-specific telemetry that is read out through a standard interface for 3rd party silicon analytics platforms.
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