The G2 AES encryption core represents the second generation of Algotronix' AES technology: it is a stable, NIST validated implementation of the entire algorithm as specified in NIST publications FIPS197 and SP800-38A and includes an implementation of the entire NIST AESAVS test suite.
Algotronix can also provide a design service to extend or tailor the core to meet the specific requirements of your application.
- Fully synchronous with single clock and enable
- Configurable via VHDL generic parameters to trade features and performance against area
- Source code available for security review
- Cost Effective Royalty Free licencing with a variety of options to suit project requirements
- Easy to use, single clock and enable
- Enable allows pausing the core on a cycle by cycle basis for flow control
- VHDL source code
- FPGA vendor tool project directories
- Processor Interface application note
- Getting Started reference design for FPGA vendor evaluation boards
- The 32 bit data path used in this core is suitable for securing low to medium speed communications - up to 500Mbit/sec depending on the target FPGA. For 500Mbit to 3Gbit applications our G3 core with a 128 bit datapath can be used and for 3 - 100Gbits one of our pipelined cores is required.