The NIST Validated (cert # 953) G3 AES core family is the third generation of Algotronix' AES technology. The G3 core is designed without compromise to be the most efficient and flexible implementation of AES available. A significant enhancement in the G3 product line is that the widths of internal and external data paths can be selected by the user using compilation parameters to allow an optimal tradeoff between area and performance. The G3 core thus supports a full range of AES implementations from ultra small cores targetting a CPLD to multi-gigabit parallelised cores running on advanced FPGAs. The G3 core also features an optimised implementation of the AES algorithm which allows it to encrypt or decrypt a block of data in fewer clock cycles than competitive products. G3 is supplied with a comprehensive testbench implementing the AESAVS test suite. The testbench can run qualification vectors from a NIST approved laboratory to provide an easy path to validation for user products using AES G3.
The G3 core is available as VHDL or Verilog source code.
Algotronix can also provide a design service to extend or tailor the core to meet the specific requirements of your application.
- Configurable data path width.
- Keyschedule calculation can be overlapped with data processing.
- Calculates AES in fewer clock cycles than competitive products.
- Extremely flexible. With a multi-project licence there will be many opportunities to make use of the core.
- VHDL Source code and testbench
- Low to Medium speed applications from 10Mbit/sec (configured with 8 or 16 bit datapath) to 3 Gbit/sec (configured with 128 bit datapath). For applications above 3Gbit/sec one of our pipelined products is required.