This state of the art implementation of AES-GCM achieves 10Gbit/sec performance under worst case traffic conditions on Virtex 5 FPGAs. It implements AES-GCM as specified by the IEEE 802.1ae MACSEC standard.
Achieving 10Gbit/sec throughput on minimum sized packets with minimum inter-packet separation is a challenging task, particularly for an FPGA implementation where there are limitations on maximum clock frequency. The conventional approach to providing high performance on AES is to use a deep pipeline however this is ineffective on worst case traffic since minimum sized packets do not contain enough data to fill the pipeline. This core implements a pipelined and overlapped architecture with a number of proprietary implementation optimisations to deliver the required 10Gbit/sec performance even on worst case traffic. This core was developed to meet the requirements of a leading vendor of IP network test equipment and is currently in production.
This core is supplied as VHDL source code with a testbench which implements standard vectors from the GCM specification and a large test suite of vectors derived from a software implementation of AES-GCM.
- Data path width is configurable to match resource use to required throughput
- GCM mode provides authentication and privacy where most simple AES modes provide only privacy. Unlike the Counter with CBC MAC (CCM) mode used in many wireless networking standards and also available from Algotronix GCM can be parallelised to achieve multi-gigabit data rates.
- VHDL or Verilog Source Code for GCM mode
- Testbench which implements all use cases in GCM proposal and much larger test cases created by an Algotronix software implementation of AES-GCM
- AES G3 core and testbench
- This core is suitable for low to medium speed applications requiring AES -GCM up to around 1Gbit/sec. For higher speed applications our pipelined AES-GCM products are required.