AES core

Features

• Implemented according to the FIPS 197 documentation.
• Also available in CBC, CFB and OFB modes.
• Key size of 128, 192 and 256 bits.
• Both encryption and decryption supported.
• Fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core.
• Test benches provided.
• Xilinx and Altera netlists available.

Deliverables

• Available as fully functional and synthesizable VHDL or Verilog soft-core.
• Test benches provided.
• Xilinx and Altera netlists available.

• see the entire AES core datasheet
• get in contact with AES core Supplier