AES core
Features
- Implemented according to the FIPS 197 documentation.
- Also available in CBC, CFB and OFB modes.
- Key size of 128, 192 and 256 bits.
- Both encryption and decryption supported.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
- Test benches provided.
- Xilinx and Altera netlists available.
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AES core IP
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