This highly configurable implementation of the XTS-AES algorithm for storage encryption implements the full NIST SP800-38E specification used in IEEE standard 1619-2007. AES XTS is based on a pipelined implementation of AES to provide throughput to match multi-gigabit storage connection schemes such as USB 3.0 and SATA 3.0.
The AES-XTS core is based on our NIST validated AES-G3 implementation and is supplied as a complete package of VHDL or Verilog source code. The number of pipelined AES encryptors is configurable allowing a flexible tradeoff of area against performance.
- Complies with IEEE 1619-2007 and NIST SP800-38E standards
- Performance selectable to meet or exceed USB 3.0 and SATA 3.0 (6 Gbps), even on low cost FPGA families
- Low area, implementation of AES-XTS suitable for data storage applications.
- Based on the NIST validated (Cert #953) AES-G3 implementation of FIPS 197 (November 2001) Advanced Encryption Standard
- Supports 128 bit keys as standard, with 192 and 256 bit key options available
- Targets all modern FPGA families from Xilinx, Altera, Microsemi and Lattice.
- Supplied as easily customizable portable VHDL or Verilog to allow customers to conduct their own code review in high-security applications.
- Supplied with comprehensive test bench implementing XTSVS tests
- VHDL with Testbench.
- optimizations for Xilinx, Altera, Lattice and Microsemi FPGAs.
- Disk and USB drive encryption.
- Encryption with resistance to tampering where data expansion is not possible so authentication methods which involve appending an integrity check value cannot be used.