This is an AES based encryption processor supporting the widely accepted protocols of CCM and GCM. CMAC (as specified in 802.11) is also supported.
The processor consists of one or more AES cores, a GHASH block (for the GCM option), scheduling controllers and datapath steering logic to manage the AES/GHASH resources to implement the required protocol (CCM, GCM etc).
IO is in the form of 128 bit blocks. External logic is required to map the blocks to the required system level bit-width.
Hardware signals provide the encryption key, nonce (or initialization vector) and byte counts for the nonce (N), MIC (M), additional (A) data and payload (P) data. A keyMode signal 0-2 selects a key size of 128, 256, 512 bits. A mode signal selects the protocol (CCM, CMAC, GCM) and also allows selection of 'raw' AES modes (CBC, CTR, ECB). An encrypt signal selects between encryption and decryption (not supported for ECB and CBC modes).
The aforementioned signals are static and may easily be mapped to memory mapped registers in your system. A recommended mapping is provided however we leave the implementation to you as this is system-specific. Likewise the mapping of the 128-bit IO blocks to your internal data-path is architecture specific and also often requires standard-specific manipulation of headers (typically done in software).