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PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
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Basic AES Accelerator
The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O registers, encryption and decryption cores, and the logic for feedback modes and key scheduling.
Designed for fast integration, low gate count, and maximum performance, the AES Engines provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs.
Designed for fast integration, low gate count, and maximum performance, the AES Engines provide a reliable and cost-effective AES IP solution that is easy to integrate into SoC designs.
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