AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
View AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length full description to...
- see the entire AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length datasheet
- get in contact with AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length Supplier
AES IP
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- FortiCrypt AES SX Series IP Core
- Tunable AES (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
- AES-ECB-CBC-CFB-OFB-CTR-GCM-XTS-CCM Crypto Accelerator
- DPA Resistant AES Core
- AES + SHA DMA Crypto Accelerator