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AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length
The use of IP cores in ASIC, FGPA and system-on-chip (SoC)design has become a critical methodology as companies struggle to address the need for rapid prototyping and production. Reusable, drop-in components with pre-defined functionality, IP cores speed the design cycle, increase design quality and allow a greater degree of innovation, enabling companies to reduce design costs and create market differentiation.HDL Design House provides a set of IP cores for reuse along with IP core customization services to meet specific customer needs. Optimized for today’s SoC designs, these IP cores are supported with full documentation, including architectural and micro-architectural specifications, synthesis scripts, detailed test plans, test case definitions and test bench descriptions.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
Features
- Fully compliant with 128/192/256 bit keys and 128 bit data AES (Rijndael) algorithms according to NIST FIPS PUB 197.
- Supports Electronic Code Book (ECB) and Cipher Block Chaining (CBC) modes of operation.
- Pipeline operation in ECB mode.
- Software configurable IP core through 22 32 bits registers. Fixed 32 bits length to all architecture registers.
- 16 maskable interrupts.
- Dedicated DMA and FIFO for both input and output data paths.
- OCP 2.2 bus interface core variant with separated OCP agents for input/output DMA transfers.
- 12.8Gb/s average data transfer rate.
- AHB AMBA bus interface core variant.
- Two independent and synchronous FIFOs (16x128 bits) closely coupled with AES engine with concurrent read/write operations for input/output data streams.
- Bus-Matching (programmable data path width) x8/x16/x32/x64/x128 bits for input and output DMA transfers. Can be programmed by software during IP core operation.
- Power down mode of the operation for low power applications.
- Available in both Verilog and VHDL.
- VITAL 2000 and SystemC behavioral models.
- DFT support implemented.
Benefits
- Basic license - gate level netlist for requested technology.
- Full license - RTL code with the deliverables specified bellow.
- Full details upon customer's request.
Deliverables
- Verilog, VHDL, SystemC code.
- Testbench and test cases code.
- Scripts to run simulations and regression.
- Synthesis scripts.
- Documentation, that includes:
- Microarchitectural specification;
- Testbench and test cases definitions;
- Test reports.
- Architectural specification
- Integration manual
- VITAL 2000 models for system simulation.
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