AES - Full hardware implementation of NIST FIPS PUB 197 algorithm. 128 bit data and programable 128/192/256 key length

The use of IP cores in ASIC, FGPA and system-on-chip (SoC)design has become a critical methodology as companies struggle to address the need for rapid prototyping and production. Reusable, drop-in components with pre-defined functionality, IP cores speed the design cycle, increase design quality and allow a greater degree of innovation, enabling companies to reduce design costs and create market differentiation.HDL Design House provides a set of IP cores for reuse along with IP core customization services to meet specific customer needs. Optimized for today’s SoC designs, these IP cores are supported with full documentation, including architectural and micro-architectural specifications, synthesis scripts, detailed test plans, test case definitions and test bench descriptions.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.

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