AES-XTS encryption/decryption IP

SphinX is designed to accommodate the speed, latency and throughput requirements of high performance computer systems main memory / DRAM. The IP implements the standard (NIST FIPS 197) AES cipher in XTS mode (IEEE Std 1619-2018). The SphinX family of cores covers a scalable IP with 128b and 256b key support, allowing the designer to choose the most efficient and effective core that satisfies the latency and throughput requirements.
The design is fully synchronous and supports independent, non-blocking encryption/decryption at main memory speed. SphinX is available for immediate licensing.

References:
IEEE Std 1619-2018, IEEE Standard for Cryptographic Protection of Data on Block-Oriented Storage Devices https://standards.ieee.org/standard/1619-2018.html
NIST FIPS 197, Advanced Encryption Standard (AES) https://www.nist.gov/publications/advanced-encryption-standard-aes

• see the entire AES-XTS encryption/decryption IP datasheet
• get in contact with AES-XTS encryption/decryption IP Supplier