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AES-XTS Multi-Booster
The AES-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the AES algorithm making the solution suitable for a wide range of low-cost & high-end applications (including key, tweak, input and output registers and Galois field multiplier).
This crypto engine targets high-performance applications, where a high throughput is required. Thanks to its scalability, it can be tailored to reach the best trade-off between performances, area and technology.
Overview
The AES-XTS crypto engine is easily portable to ASIC and FPGA . It supports a wide range of applications on various technologies. The unique architecture enables a high level of flexibility. The throughput and features required by a specific application can be taken into account in order to select the most optimal and compact configuration.
For other AES solutions, please see dedicated product sheets: AES Multi-Purpose (BA411e) and AES-GCM Multi-Booster (BA415)
This crypto engine targets high-performance applications, where a high throughput is required. Thanks to its scalability, it can be tailored to reach the best trade-off between performances, area and technology.
Overview
The AES-XTS crypto engine is easily portable to ASIC and FPGA . It supports a wide range of applications on various technologies. The unique architecture enables a high level of flexibility. The throughput and features required by a specific application can be taken into account in order to select the most optimal and compact configuration.
For other AES solutions, please see dedicated product sheets: AES Multi-Purpose (BA411e) and AES-GCM Multi-Booster (BA415)
Features
- ASIC and FPGA
- High throughput:
- ASIC: 2Tbps
- FPGA: 100 Gbps/s
- Scalable solution
- Supports 128-bit & 256-bit key
- Compliant with NIST SP800-38E
- Can be provided with AXI DMA & software
- Masking option available with excellent protection against SPA & DPA
- Cipher stealing (optional)
- Low power feature
- Straight forward integration with simple FIFO interfaces
Benefits
- Off-the-shelf, predictable and silicon-proven solution
- Easy-to-Integrate
- Unrivaled speed performance
- Logic footprint optimized to performance requirements and used functionalities
- Scalable Multi-Core solution enabling best trade-off between area and performance
- Portable and optimized to ASIC or FPGA technology
- Upgradeable to new performance requirements or to new generations of ASIC or FPGA technology
- User-friendly Software API
Deliverables
- Netlist or RTL
- Scripts for synthesis
- Self-checking TestBench based on FIPS vectors
- Datasheet
- Integration guide
Applications
- Encrypted Disk/Data storage
- SATA III
Block Diagram of the AES-XTS Multi-Booster IP Core
View AES-XTS Multi-Booster full description to...
- see the entire AES-XTS Multi-Booster datasheet
- get in contact with AES-XTS Multi-Booster Supplier
AES IP
- UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
- AES-GCM Multi-Booster
- DPA Resistant AES Core
- Symmetric Cryptography Engine: High Performance AES-GCM/CTR IP Core
- Symmetric Cryptography Engine: High Performance AES-GCM/CTR IP Core
- INSIDE Secure 800G Multi-Channel MACsec Engine