The IGDNET001A (UINF0201) is a 10/100Mbps AHB Ethernet MAC. It includes AHB wrapper, DMA engine, on-chip memory (TX/RX FIFO), TX MAC, RX MAC and MII interface.
The DMA handles the data transfer between system memory and on-chip memory. With DMA engine, it will reduce CPU loading and enhance performance. An industry-standard interface is necessary for reusable reason. It is fully compliant with AMBA 2.0 and IEEE802.3u Standard. An AHB wrapper provides the transfer between GUC internal interface, BII (Bus Independent Interface) and AHB interface.
The memory size always dominates the hardware cost. For this reason, the FIFO size is configurable (128-Byte ~ 2K-Byte), dependent on userሙs application or system bus performance.
- * Comply with AMBA specification 2.0
- * AHB bus with Master and Slave mode
- * AHB with programmable bust size
- * Serial ROM interface support
- * PHY management interface MDIO support
- * Comply with IEEE 802.3u MII interface
- * Full /Half Duplex capability
- * Support IEEE 802.3x Full Duplex Flow Control
- * Support IEEE 802.1Q VLAN mode
- * Support Loopback test mode
- * Includes two DMA to reduce CPU loading
- * Independent TX and RX FIFO
- * Configurable FIFO size (128B~2KB)
- * Embedded Memory BIST block