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Dual thread, superscalar, embedded 32-bit RISC-V core with 9-stage pipeline
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AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defined in the AMBA 3 AHB-Lite v1.0 specifications are fully supported.
The IP supports a single AHB-Lite based host connection and enables address & data widths, memory depth & target technology to be specified via parameters. An option to register the memory output is also provided.
The IP supports a single AHB-Lite based host connection and enables address & data widths, memory depth & target technology to be specified via parameters. An option to register the memory output is also provided.
Features
- Full support for AMBA 3 AHB-Lite protocol
- Fully parameterized
- User-defined address and byte-aligned data widths supported
- Configurable memory depth, limited only by target technology capability
- Technology-specific memory cells instantiated automatically
- Combinatorial or registered data output
Benefits
- Design to support any silicon technology
Deliverables
- Full Source Code
- Testbenches
- Compilation Scripts
- Documentation
Block Diagram of the AHB-Lite General Purpose Memory Module IP Core
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AHB-Lite Memory IP
- I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- Flash Memory pre-fetcher controller with AHB lite system
- Peripheral Direct Memory Access Controller
- I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
- Display Controller - LCD / OLED Panels (AHB-Lite Bus)