USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm, 6nm)
The IP features an AHB-Lite Slave interface, with all signals defined in the AMBA 3 AHB-Lite v1.0 specifications fully supported, supporting a single AHB-Lite based host connection. Bus address & data widths as well as the number of timers supported are specified via parameters.
The timebase of the timers is derived from the AHB-Lite bus clock, scaled down by a programmable value.
The module features a single Interrupt output which is asserted whenever an enabled timer is triggered
View AHB-Lite Timer full description to...
- see the entire AHB-Lite Timer datasheet
- get in contact with AHB-Lite Timer Supplier
Block Diagram of the AHB-Lite Timer IP Core
AHB-Lite Timer IP
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