The CoreAHBLtoAXI is an AHBLite slave and an AXI master that provides an interface (bridge) between the AHB domain and AXI domain. The CoreAHBLtoAXI allows an AHBLite bus system to be connected to an AXI bus. The AHBLite to AXI Bridge enables the AHBLite master to communicate with AXI slave. It allows the AHBL bus to initiate data transfer between the two buses. The AHBL slave interface and AXI master interface allows the AHBL bus and AXI bus to access the read/write buffer memory.
- An interface (bridge) between the AHB domain and AXI domain
- SINGLE/INCR/WRAP type write transactions
- SINGLE/INCR/WRAP type read transactions
- WRAP type transactions for word size accesses only. WRAP for half word and byte size accesses are not supported in this release
- Undefined length Increment bursts on the AHBL are converted only into single burst transfer. INCR transactions of 64-bit size and burst length UPTO 16 are not supported in this release