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eUSB 3.1 Gen 2 Device Controller - Software Enumeration, FIFO Interface
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AMBA 5 / AXI / ACE / ACE-lite / CHI NoC monitor
Embedded Analytics supports non-intrusive monitoring and smart analytics of standard interconnects from the Arm ecosystem, including AXI, ACE, ACE-lite, and AMBA 5 CHI (Coherent Hub Interface).
Our IP enables full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. In addition, the modules can track transactions (eg trace) and automatically gather statistics (to identify issues such as contention, peak traffic, and deadlock).
The CHI Monitor extends that from bus monitors to debugging and fine-tuning the NoC (Network on Chip) fabric and visibility of the SoC as a whole.
The CHI NoC Monitor module permits detailed real-world monitoring and analysis of the functioning of the interconnect, allowing chip developers to understand its performance and optimize overall SoC performance. It is the market’s only fully-featured CHI debug solution, providing better visibility and analytics than can be achieved with legacy debug solutions such as ARM’s own CoreSight product.
Our IP enables full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. In addition, the modules can track transactions (eg trace) and automatically gather statistics (to identify issues such as contention, peak traffic, and deadlock).
The CHI Monitor extends that from bus monitors to debugging and fine-tuning the NoC (Network on Chip) fabric and visibility of the SoC as a whole.
The CHI NoC Monitor module permits detailed real-world monitoring and analysis of the functioning of the interconnect, allowing chip developers to understand its performance and optimize overall SoC performance. It is the market’s only fully-featured CHI debug solution, providing better visibility and analytics than can be achieved with legacy debug solutions such as ARM’s own CoreSight product.
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AXI IP
- AXI DMA Back-End Core
- AXI Interface Core
- PCIe 5.0 Controller with AMBA AXI interface
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
- PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect