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AMBA 5 / AXI / ACE / ACE-lite / CHI NoC monitor
UltraSoC supports non-intrusive monitoring and smart analytics of standard interconnects from the Arm ecosystem, including AXI, ACE, ACE-lite, and AMBA 5 CHI (Coherent Hub Interface).
Our IP enables full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. In addition, the modules can track transactions (eg trace) and automatically gather statistics (to identify issues such as contention, peak traffic, and deadlock).
The CHI Monitor is the newest in UltraSoC’s family of protocol-aware monitors for interconnect, and extends that from bus monitors to debugging and fine-tuning the NoC (Network on Chip) fabric and visibility of the SoC as a whole.
The CHI NoC Monitor module permits detailed real-world monitoring and analysis of the functioning of the interconnect, allowing chip developers to understand its performance and optimize overall SoC performance. It is the market’s only fully-featured CHI debug solution, providing better visibility and analytics than can be achieved with legacy debug solutions such as ARM’s own CoreSight product.
Our IP enables full transaction-level visibility of traffic on buses with a wide range of measurements, analytics and statistics gathering. All of these are highly configurable and include “logic analyzer” style controls and dependencies, local buffering and cross-triggering. In addition, the modules can track transactions (eg trace) and automatically gather statistics (to identify issues such as contention, peak traffic, and deadlock).
The CHI Monitor is the newest in UltraSoC’s family of protocol-aware monitors for interconnect, and extends that from bus monitors to debugging and fine-tuning the NoC (Network on Chip) fabric and visibility of the SoC as a whole.
The CHI NoC Monitor module permits detailed real-world monitoring and analysis of the functioning of the interconnect, allowing chip developers to understand its performance and optimize overall SoC performance. It is the market’s only fully-featured CHI debug solution, providing better visibility and analytics than can be achieved with legacy debug solutions such as ARM’s own CoreSight product.
Features
- Full transaction and trace-level visibility of on-chip bus traffic
- Wide range of measurements, analytics and stats gathering
- Transactions
- Bus cycles
- Latency
- Duration
- Bytes
- Beats
- Bus concurrency
- Trace
- Highly configurable
- Logic analyzer style controls and dependencies
Benefits
- Faster chip bring-up
- Faster debug cycles - lower cost
- Spot hard-to-identify bugs
- Monitor and performance tune sophisticated coherent interconnects
- Better visibility and analytics
Deliverables
- Parameterised soft core
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AXI IP
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- XpressCCIX-AXI Controller IP for PCIe 5.0 with CCIX ESM support
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- FlexNoC Network on Chip SoC Interconnect IP
- FlexNoC Resilience Package IP
- Timing Closure Package