Die-to-Die, 112G Ultra-Extra Short Reach PHY in TSMC (12nm, N7, N6, N5)
AMBA AHB 4 Channel DMA Controller
Once configured and enabled, the DMA controller is primarily an AHB Master, which initiates data transfers across the AHB bus to/from a peripheral device through the DMA Buffer. The DMA Buffer is a 16x32-bit FIFO, which is useful for peripheral devices requiring a steady stream of data such as an LCD Controller, Ethernet MAC or other communication device.
The DMA controller contains useful features such as incrementing and non-incrementing addressing and link list operation. Linked list support is useful for non-contiguous memory transfer operations.
The DMA Channel Arbiter determines which DMA Channel has access to the external AHB Master Bus. A round-robin algorithm is implemented in which each active channel has equal priority.
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