The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus. This gives added visibility to the software in order to debug address related issues in an SoC in simulation or on a fabricated chip. In the event of an address that does not decode to a defined slave, the access should be redirected towards an instance of the Address Trapper by the AHB decoder in the AHB bus controller. The faulty address and master number is captured and stored in a FIFO of configurable depth. The FIFO contents can be read out by the CPU over the APB interface. The CPU can receive an interrupt event to indicate that the FIFO contains debug information.