CoreAHBLite is a multi-master implementation of the AHB-Lite bus interconnect (a subset of the AMBA advanced high-performance bus) used to connect subsystem cores to Microsemi's 32-bit ARM processors. CoreAHBLite provides 2 AHB-Lite master interfaces, 16 AHB-Lite slave interfaces plus an optional seventeenth AHB-Lite slave interface in a huge 2 GB memory space (231 bytes), and up to 16 Init/Config master interfaces that can be used to initialize up to 16 FPGA SRAM instances. Each slave can either be enabled or disabled for each master via the configuration GUI (graphical user interface). Bus slaves that are not enabled in the configuration GUI are optimized away during synthesis, and if no slaves are selected for a given master, that master interface will be disabled and optimized away during synthesis, yielding ideal compact implementations in FPGA fabric.
CoreAHBLite is small in size and allows easy connection of IP cores in ARM-based systems on Microsemi FPGAs. CoreAHBLite is small in size and allows easy connection of IP cores in ARM-based systems on Microsemi FPGAs.