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AMBA AXI Data Writer Spreader
The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data may need to be spread into different address ranges. The data is input to a FIFO. The parameters for the destination addresses are configured by way of the APB bus. The destination address is calculated in two dimensions.
Features
- Easy integraton
- AMBA AXI 3.0 Compatible
- Configurable FIFO depth
- Programmable Destination address parameters
- 2 dimensional address calculation
- Input data FIFO with configurable depth
- Data input width 64-bit
- AXI write data width 64-bit
- APB interface for configuration and status
- Software reset
- Configurable AXI bursts
- Event Interrupt Indication
Benefits
- Low Gate Count
- Low Power Consumption
- Spyglass Lint Validated
- Standards Compliant
Deliverables
- Synthesizable Verilog RTL
- Detailed block diagram and technical documents
Applications
- General System on Chip Use
Block Diagram of the AMBA AXI Data Writer Spreader IP Core
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- PCI Express (PCIe) Gen4 x4
- PCI Express (PCIe) Gen4 x8
- PCI Express (PCIe) Gen4 x16
- Configurable PCI Express 4.0 Controller for ASIC/SoC with a configurable AMBA AXI3/AXI4 user interface
- Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC with AMBA AXI User Interface
- FlexWay Interconnect IP for design teams who use multilayer AMBA AHB