The AMBA DMA Controller core is designed to purposefully integrate most FIFO standard interfaces from a MAC or SWITCH used for Ethernet frame transmission, with a processor CPU sub-system. It is traditionally the approach to let the systems integrator have to deal with implementing a processor DMA Master (or individual CPU memory accesses) to read/write the FIFO data. By having an AXI Master with an IP core, it is the hardware associated with the FIFO that is controlling the placement and transfer of receiving/transmitting Ethernet frames – thus emphasizing the major difference of this DMA core to the standard approach of most CPU architectures utilizing the memory DMAs normally available. The DMA can be used in Network Interface cards or Ethernet switching applications. It is totally agnostic to specific MAC hardware or the processor sub-system.
Whilst not compulsory or statutory, a Linux device driver is available with this product to ensure that the core can be easily used with a demanding and realistic platform used by more and more designers.
The DMA core on the processor side, implements a 32-bit or 64-bit data bus width and 32-bit address bus both synchronous to the memory bus clock. With the FIFO interface on the other side having the same data width attributes, the DMA core is incredibly efficient giving the product its fundamental purpose – to access to processor memory device with Ethernet frame data at a vastly superior rate to standard DMA methods. The DMA core is delivered either in generic Verilog synthesizable DHL code for ASIC or FPGA implementations, or in an encrypted format for FPGA implementations.