The AMBA DMA Controller core is designed to purposefully integrate most FIFO standard interfaces from a MAC or SWITCH used for Ethernet frame transmission, with a processor CPU sub-system. It is traditionally the approach to let the systems integrator have to deal with implementing a processor DMA Master (or individual CPU memory accesses) to read/write the FIFO data. By having an AXI Master with an IP core, it is the hardware associated with the FIFO that is controlling the placement and transfer of receiving/transmitting Ethernet frames – thus emphasizing the major difference of this DMA core to the standard approach of most CPU architectures utilizing the memory DMAs normally available. The DMA can be used in Network Interface cards or Ethernet switching applications. It is totally agnostic to specific MAC hardware or the processor sub-system.
Whilst not compulsory or statutory, a Linux device driver is available with this product to ensure that the core can be easily used with a demanding and realistic platform used by more and more designers.
The DMA core on the processor side, implements a 32-bit or 64-bit data bus width and 32-bit address bus both synchronous to the memory bus clock. With the FIFO interface on the other side having the same data width attributes, the DMA core is incredibly efficient giving the product its fundamental purpose – to access to processor memory device with Ethernet frame data at a vastly superior rate to standard DMA methods. The DMA core is delivered either in generic Verilog synthesizable DHL code for ASIC or FPGA implementations, or in an encrypted format for FPGA implementations.
- Flexible DMA controller to attach MorethanIP FIFO interfaces to AXI memory bus from host processor.
- Support flexible data bus width of 32-bit and 64-bit system memory busses.
- Support flexible FIFO data width of 32-bit and 64-bit to the associated Ethernet hardware cores.
- Supports four independent channels (two RX and two TX), for ingress (FIFO to bus) and for egress (bus to FIFO) data transfers.
- Three Independent AMBA Interfaces;
- AHB-Lite Control Block to allow internal and external register access for control
- AXI Write Master (TX) to transfer data from memory to FIFO interface.
- AXI Read Master (RX) to transfer data from FIFO interface to memory.
- Fully independent (parallel) operation of Egress (TX) and Ingress (RX) channels.
- Up to 128-bit of control and status XSTAT (side-band) in formation transferred transparently with frames for arbitrary use by system and application (e.g. timestamps)
- Flexible interrupt support for efficient transmit and receive handshaking.
- Pass-through ability to SWITCH/MAC for hardware calculation of UDP/TCP header checksum removing CPU processor burden per packet.
- IO-Register control/status with MUX providing throughput access to cascaded hardware cores.
- Programmable maximum frame length of 64K to support Jumbo frames
- Fully agnostic design to support variable processor architecture, variable IP core hardware and Ethernet features.
- Prioritization of the two RX channels allow CH0 to be processed over CH1 enabling higher priority packet discrimination to boost functional performance of the application software.
- Prioritization of the two TX channels allow CH0 to be processed over CH1 enabling higher priority packet discrimination to boost functional performance of the application software.
- Single IRQ channel from the DMA to the host processor sub-system environment. This allows for simpler device driver handling of DMA related events whilst at the same time, multiplexing all DMA events and external hardware into one output signal.
- RX DMA Back pressure FIFO to allow for compatibility with MACs that have a latent response to DMA ready signal. The FIFO will store incoming Ethernet octets beyond the ready signal de-activating during the latent period.
- Optionally provided Linux device driver to allow for ready-torun software platform able to harness and take advantage of the DMA hardware in FPGA or ASIC.
- Verilog synthesizable RTL or encrypted RTL for FPGA implementation
- Behavioral Verilog test benches and verification test cases
- Support for FPGA and ASIC design tools
- Optional Linux device driver or basic generic C-source functions
Block Diagram of the AMBA DMA AXI Controller IP Core